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OUTLINE
'04.04.23
4-wire Serial Interface
R2043K/T
The R2043K/T is a CMOS real-time clock IC connected to the CPU by four signal lines, CE, SCLK, SI, SO, and configured to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.45A at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output function (N-channel open drain output) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0: R2043T) or FFP12 (2.0x2.0x1.0: R2043K), high density mounting of ICs on boards is possible.
FEATURES
Minimum Timekeeping supply voltage TYP:0.66 to 5.5v (Worst: 1.00V to 5.5v); VDD pin Low power consumption 0.45A TYP at VDD=3V (1.00A MAX.) Four signal lines (CE, SCLK, SI, and SO) required for connection to the CPU. Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format) Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings) With Power-on flag to prove that the power supply starts from 0V 32-kHz clock output pin (N-channel open drain output) Supply voltage monitoring circuit with two supply voltage monitoring threshold settings Automatic identification of leap years up to the year 2099 Selectable 12-hour and 24-hour mode settings High precision oscillation adjustment circuit Built-in oscillation stabilization capacitors (CG and CD) Package TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2043T) FFP12 (2.0mm x 2.0mm x 1.0mm: R2043K) CMOS process
PIN CONFIGURATION
R2043T(TSSOP10G)
R2043K(FFP12)
OSCOUT OSCIN
CE
32KOUT SCLK SO SI VSS
1 2 3 4 5
10 9 8 7 6
VDD OSCIN OSCOUT CE /INTR
/INTR VSS SI
8 2
10 11 12 1 3
SO
SCLK
TOP VIEW
TOP VIEW
32KOUT
9
7 6 5 4
VDD (VSS) (VSS)
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R2043K/T
BLOCK DIAGRAM
ALARM_W REGISTER (MIN,HOUR, WEEK) ALARM_D REGISTER (MIN,HOUR) VOLTAGE DETECT POWER_ON RESET VSS
32KOUT
32kHz OUTPUT CONTROL
COMPARATOR_W
VDD
COMPARATOR_D OSCIN OSC OSCOUT
DIVIDER CORREC -TION
DIV
TIME COUNTER (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
OSC DETECT
ADDRESS DECODER
ADDRESS REGISTER
SCLK I/O CONTROL SI SO
/INTR
INTERRUPT CONTROL
SHIFT REGISTER
CE
SELECTION GUIDE
Part Number is designated as follows: R2043K-E2 Part Number R2043a-bb Code a bb Description Designation of the package. K: FFP12 T: TSSOP10G Designation of the taping type. Only E2 is available.
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PIN DESCRIPTION
Symbol CE Item Chip enable Input Description The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SI and SO pins. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SI pin is used to input data intended for writing in synchronization with the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SO pin is used to output data intended for reading in synchronization with the SCLK pin. CMOS output. If the CE pin is low, the SO pin goes to a high impedance state. The /INTR pin is used to output alarm interrupt (Alarm_W) and alarm interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage. The 32KOUT pin is used to output 32.768-kHz clock pulses. The pin is N-channel open drain output. However it cannot be pulled up over VDD+0.3v. The OSCIN and OSCOUT pins are used to connect the 32.768-kHz crystal oscillator (with all other oscillation circuit components built into the R2043K/T). The VDD pin is connected to the power supply. The VSS pin is grounded.
SCLK
Serial Clock Input Serial Input
SI
SO
Serial Output
/INTR
Interrupt Output
32KOUT
32kHz Clock Output Oscillation Circuit Input / Output Positive/Negative Power Supply Input
OSCIN OSCOUT VDD VSS (VSS)
Please connect to ground line, or do not connect any lines.
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO PD Topt Tstg Item Supply Voltage Input Voltage Output Voltage 1 Output Voltage 2 Power Dissipation Operating Temperature Storage Temperature Pin Name VDD CE, SCLK, SI SO, 32KOUT /INTR Topt = 25C (VSS=0V) Description -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +6.5 300 -40 to +85 -55 to +125 Unit V V V V mW C C
RECOMMENDED OPERATING CONDITIONS
Symbol Vaccess Item Supply Voltage Pin Name Power supply voltage for interfacing with CPU CGout,CDout=0pF *1), *2) CGout,CDout=0pF *1), *2) /INTR 32KOUT Min, 1.7 *1) 1.00 0.66 32.768 (VSS=0V, Topt=-40 to +85C) Typ. Max. Unit 5.5 V
VCLK VCLKL fXT VPUP
Time keeping Voltage Minimum Time keeping Voltage Oscillation Frequency Pull-up Voltage
5.50 1.00
V
kHz 5.5 V VDD +0.3 *1) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2043K/T series incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout and CDout are not necessary. For more detail, see "P.28 Adjustment of Oscillation frequency" *2) Crystal oscillator: CL=6-9pF, R1=50K
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DC ELECTRICAL CHARACTERISTICS
R2043K/T (Unless otherwise specified: VSS=0V, VDD=3.0V, Topt=-40 to +85C, Crystal oscillator 32768Hz,CL=7pF,R1=50k) Symbol Item Pin Name Conditions Min. Typ. VIH "H" Input Voltage 0.8x CE, VDD=1.7 to 5.5V VDD SCLK, SI VIL "L" Input Voltage -0.3 IOH IOL1 IOL2 IIL RDNCE IOZ1 IOZ2 IOZ3 IDD Time Keeping Current "H" Output Current "L" Output Current Input Leakage Current Pull-down Resistance SO /INTR SO, 32KOUT SI, SCLK CE SO /INTR 32KOUT VDD VOH=VDD-0.5V VOL=0.4V 2.0 0.5 -1.0 40 -1 -1 -1 120 1.0 400 1 1 1 A
Max. 5.5 0.2x VDD -0.5
Unit V
mA
mA A k A
VI=5.5V or VSS VDD=5.5V VO=5.5V or VSS VDD=5.5V VO=5.5V VDD=5.5V VO=5.5V VDD=5.5V VDD=3V, CE= OPEN Output = OPEN 32KOUT=OFF CGout=CDout=0pF *1) Topt=-30 to +70C
Output Off-state Current
0.45
1.00
VDETH
Supply Voltage VDD 1.45 1.60 1.75 V Monitoring Voltage "H" VDETL Supply Voltage VDD 1.15 1.30 1.45 V Topt=-30 to +70C Monitoring Voltage "L" *1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see "P.43 Typical Characteristics". For time keeping current when CGOUT, CDOUT is not equal to 0pF, see "P.28 Adjustment of Oscillation frequency".
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AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 to +85C Input and Output Conditions: VIH=0.8xVDD,VIL=0.2xVDD,VOH=0.8xVDD,VOL=0.2xVDD,CL=50pF Symbol Item CondiUnit VDD1.7V tions Min. Typ. Max. tCES CE Set-up Time 400 ns tCEH CE Hold Time 400 ns tCR CE Recovery Time 62 s fSCLK SCLK Clock Frequency 1.0 MHz tCKH SCLK Clock High Time 400 ns tCKL SCLK Clock Low Time 400 ns tCKS SCLK Set-up Time 200 ns tRD Data Output Delay Time 300 ns tRZ Data Output Floating Time 300 ns tCEZ Data Output Delay Time 300 ns After Falling of CE tDS Input Data Set-up Time 200 ns tDH Input Data Hold Time 200 ns
tCKH CE tCKS SCLK tCES
tCKL tCEH tCR
tDS SI SO
tDH tCEZ
tRD
tRD
tRZ
*) For reading/writing timing, see "P.28
Adjustment of Oscillation frequency".
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R2043K/T
PACKAGE DIMENSIONS
R2043K
9
7 6
10
1PIN INDEX
0.05
12
4 1 3 2PIN INDEX 0.35 0.35 0.25 1.0Max
0.103
0.30.15
0.5
0.20.15
0.5
(BOTTOM VIEW) 0.170.1 0.270.15 2.00.1
unit: mm
2.00.1
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R2043K/T
R2043T
2.90.2 10 6
0 to 10
2.80.2
4.00.2
1
5 0.5 (0.75)
0.13 -0.05
+0.1
0.1 0.20.1 0.15 M
0.1 -0.05
+0.1
0.850.15
0.550.2
unit: mm
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R2043K/T
GENERAL DESCRIPTION
Interface with CPU The R2043K/T is connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output), through which it reads and writes data from and to the CPU. The CPU can be accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing high-speed data transfer to the CPU. Clock and Calendar Function The R2043K/T reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such. *) The year 2000 is a leap year while the year 2100 is not a leap year. Alarm Function The R2043K/T incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from /INTR pin, and the Alarm_D outputs also from /INTR pin. Each alarm function can be checked from the CPU by using a polling function. High-precision Oscillation Adjustment Function The R2043K/T has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to 1.5ppm or 0.5ppm at 25C) from the CPU. The maximum range is approximately 189ppm (or 63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation frequency adjustment in each system has the following advantages: * Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with a wide range of precision variations. * Corrects seasonal frequency deviations through seasonal oscillation adjustment. * Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through oscillation adjustment in tune with temperature fluctuations. Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function The R2043K/T incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt. Power on reset function reset the control resisters when the system is powered on from 0V. At the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or battery backed-up. The R2043K/T also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can be selected between 1.6V and 1.3V through internal register settings. The sampling rate is normally 1s. The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. Periodic Interrupt Function The R2043K/T incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interrupt circuit for output from the /INTR pin. Periodic interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function. 32kHz Clock Output The R2043K/T incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
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R2043K/T
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU. The pin is N-channel open drain output, however it cannot be pulled up over VDD+0.3v.
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R2043K/T
Address Mapping
Address A3A2A1A0 00000 10001 20010 30011 40100 50101 60110 70111 81000 91001 A1 0 1 0 Register Name Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter Month Counter and Century Bit Year Counter Oscillation Adjustment Register *3) Alarm_W (Minute Register) Alarm_W (Hour Register) Alarm_W (Day-of-week Register) Alarm_D (Minute Register) Alarm_D (Hour Register) Control Register 1 *3) Control Register 2 *3) D7 *2) /1920 Y80 DEV *4) D6 S40 M40 Y40 F6 WM40 WW6 D5 S20 M20 H20 P/A D20 Y20 F5 WM20 WH20 WP/ A WW5 Data D4 D3 S10 S8 M10 H10 D10 MO10 Y10 F4 WM10 WH10 WW4 M8 H8 D8 MO8 Y8 F3 WM8 WH8 WW3 D2 S4 M4 H4 W4 D4 MO4 Y4 F2 WM4 WH4 WW2 D1 S2 M2 H2 W2 D2 MO2 Y2 F1 WM2 WH2 WW1 D0 S1 M1 H1 W1 D1 MO1 Y1 F0 WM1 WH1 WW0
B1 0 1 1 C1 1 0 0 D1 1 0 1 E1 1 1 0 F1111
WALE VDSL
DM40 DALE VDET
DM20
DM10
DM8 DH8 TEST
/CLEN1
DM4 DH4
DM2 DH2
DM1 DH1 CT0 DAFG
DH20 DH10 DP/A /1224 /CLEN2 /XST PON *5) *3)
CT2 CT1 CTFG WAFG
Notes: * 1) All the data listed above accept both reading and writing. * 2) The data marked with "-" is invalid for writing and reset to 0 for reading. * 3) PON is a power-on-reset flag. When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the /XST bit. * 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to 1.5ppm. When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to or 0.5ppm. * 5) /XST is an oscillation halt sensing monitor bit.
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Register Settings
Control Register 1 (ADDRESS Eh) D7 D6 D5 D4 D3 D2 D1 D0 WALE DALE /CLEN2 TEST CT2 CT1 CT0 (For Writing) /1224 WALE DALE /CLEN2 TEST CT2 CT1 CT0 (For Reading) /1224 0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. (1) WALE, DALE Alarm_W Enable Bit, Alarm_D Enable Bit WALE,DALE Description 0 Disabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers). 1 Enabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers)
(Default)
(2) /1224 /12-24-hour Mode Selection Bit Description /1224 0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default) 1 Selecting the 24-hour mode Setting the /1224 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode 00 12 (AM12) 12 01 01 (AM 1) 13 02 02 (AM 2) 14 03 03 (AM 3) 15 04 04 (AM 4) 16 05 05 (AM 5) 17 06 06 (AM 6) 18 07 07 (AM 7) 19 08 08 (AM 8) 20 09 09 (AM 9) 21 10 10 (AM10) 22 11 11 (AM11) 23 Setting the /1224 bit should precede writing time data (3) /CLEN2 12-hour mode 32 (PM12) 21 (PM 1) 22 (PM 2) 23 (PM 3) 24 (PM 4) 25 (PM 5) 26 (PM 6) 27 (PM 7) 28 (PM 8) 29 (PM 9) 30 (PM10) 31 (PM11)
32kHz Clock Output Bit 2 /CLEN2 Description 0 Enabling the 32-kHz clock circuit (Default) 1 Disabling the 32-kHz clock circuit Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0, specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling ("H") such output. Test Bit TEST Description 0 Normal operation mode. 1 Test mode. The TEST bit is used only for testing in the factory and should normally be set to 0.
(4) TEST
(Default)
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(5) CT2, CT1, and CT0 CT2 CT1 Periodic Interrupt Selection Bits Description CT0 Wave form Interrupt Cycle and Falling Timing mode 0 OFF(H) 1 Fixed at "L" 0 Pulse Mode 2Hz (Duty50%) *1) 1 Pulse Mode 1Hz (Duty50%) *1) 0 Level Mode Once per 1 second (Synchronized with *2) second counter increment) 1 Level Mode Once per 1 minute (at 00 seconds of *2) every minute) 0 Level Mode Once per hour (at 00 minutes and 00 *2) seconds of every hour) 1 Level Mode Once per month (at 00 hours, 00 *2) minutes, and 00 seconds of first day of every month)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
(Default)
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit
/INTR Pin Approx. 92s (Increment of second counter) Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the /INTR pin low. * 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit /INTR Pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or 60sec. as follows: Pulse Mode: The "L" period of output pulses will increment or decrement by a maximum of 3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms.
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R2043K/T
Control Register 2 (Address Fh) D7 D6 D5 D4 D3 D2 D1 D0 VDSL VDET /XST PON /CLEN1 CTFG WAFG DAFG (For Writing) VDSL VDET /XST PON /CLEN1 CTFG WAFG DAFG (For Reading) Indefinite 0 0 1 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. (1) VDSL VDSL 0 VDD Supply Voltage Monitoring Threshold Selection Bit Description Selecting the VDD supply voltage monitoring threshold setting of 1.6v. 1 Selecting the VDD supply voltage monitoring threshold setting of 1.3v. The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(Default)
(2) VDET VDET 0
Supply Voltage Monitoring Result Indication Bit Description Indicating supply voltage above the supply voltage monitoring (Default) threshold settings. 1 Indicating supply voltage below the supply voltage monitoring threshold settings. Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
(3) /XST Oscillation Halt Sensing Monitor Bit /XST Description 0 Sensing a halt of oscillation 1 Sensing a normal condition of oscillation The /XST accepts the reading and writing of 0 and 1. The /XST bit will be set to 0 when the oscillation halt sensing. The /XST bit will hold 0 even after the restart of oscillation. (4) PON Power-on-reset Flag Bit PON Description 0 Normal condition 1 Detecting VDD power-on -reset The PON bit is for sensing power-on reset condition. * * *
(Default)
The PON bit will be set to 1 when VDD power-on from 0v. The PON bit will hold the setting of 1 even after power-on. When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Register 1, and Control Register 2, except /XST and PON. As a result, /INTR pin stops outputting. The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
(5) /CLEN1 32kHz Clock Output Bit 1 /CLEN1 Description 0 Enabling the 32-kHz clock circuit (Default) 1 Disabling the 32-kHz clock circuit Setting the /CLEN1 bit or the /CLEN2 bit (D4 in the control register 1) to 0, specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the /CLEN1 and /CLEN2 bit to 1 disabling ("H") such output.
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(6) CTFG Periodic Interrupt Flag Bit CTFG Description 0 Periodic interrupt output = "H" (Default) 1 Periodic interrupt output = "L" The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTR pin ("L"). The CTFG bit accepts only the writing of 0 in the level mode, which disables ("H") the /INTR pin until it is enabled ("L") again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. (7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit WAFG,DAFG Description 0 Indicating a mismatch between current time and preset alarm time (Default) 1 Indicating a match between current time and preset alarm time The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 61s after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. /INTR pin outputs off ("H") when this bit is set to 0. And /INTR pin outputs "L" again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with the output of the /INTR pin as shown in the timing chart below.
Approx. 61s WAFG(DAFG) Bit /INTR Pin Writing of 0 to WAFG(DAFG) bit (Match between current time and preset alarm time) (Match between current time and preset alarm time) Writing of 0 to WAFG(DAFG) bit (Match between current time and preset alarm time) Approx. 61s
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Time Counter (Address 0-2h) Second Counter (Address 0h) D7 D6 D5 S40 S20 0 S40 S20 Indefinite Indefinite 0 Minute Counter (Address 1h) D7 D6 D5 M40 M20 0 M40 M20 Indefinite Indefinite 0
D4 S10 S10
Indefinite
D3 S8 S8
Indefinite
D2 S4 S4
Indefinite
D1 S2 S2
Indefinite
D0 S1 S1
Indefinite
(For Writing) (For Reading) Default Settings *)
D4 M10 M10
Indefinite
D3 M8 M8
Indefinite
D2 M4 M4
Indefinite
D1 M2 M2
Indefinite
D0 M1 M1
Indefinite
(For Writing) (For Reading) Default Settings *)
Hour Counter (Address 2h) D7 D6 D5 D4 D3 D2 D1 D0 H10 H8 H4 H2 H1 (For Writing) P/A or H20 0 0 H10 H8 H4 H2 H1 (For Reading) P/A or H20 Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) 0 0 *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. * Time digit display (BCD format) as follows: The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. The hour digits range as shown in "P12 Control Register 1 (ADDRESS Eh) (2) /1224: /12-24-hour Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from PM11 to AM12 or from 23 to 00. Any writing to the second counter resets divider units of less than 1 second. Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data.
* *
Day-of-week Counter (Address 3h) D7 D6 D5 D4 D3 D2 D1 D0 W4 W2 W1 (For Writing) 0 0 0 0 0 W4 W2 W1 (For Reading) Indefinite Indefinite Indefinite Default Settings *) 0 0 0 0 0 *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. * * * * The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. Day-of-week display (incremented in septimal notation): (W4, W2, W1) = (0, 0, 0) (0, 0, 1)...(1, 1, 0) (0, 0, 0) Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0) The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.
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Calendar Counter (Address 4-6h) Day-of-month Counter (Address 4h) D7 D6 D5 D4 D20 D10 0 0 D20 D10 Indefinite Indefinite 0 0 Month Counter + Century Bit (Address 5h) D7 D6 D5 D4 MO10 /1920 0 0 MO10 /1920 Indefinite Indefinite 0 0 Year Counter (Address 6h) D7 D6 D5 Y80 Y40 Y20 Y80 Y40 Y20
D3 D8 D8
Indefinite
D2 D4 D4
Indefinite
D1 D2 D2
Indefinite
D0 D1 D1
Indefinite
(For Writing) (For Reading) Default Settings *)
D3 MO8 MO8
Indefinite
D2 MO4 MO4
Indefinite
D1 MO2 MO2
Indefinite
D0 MO1 MO1
Indefinite
(For Writing) (For Reading) Default Settings *)
(For Writing) (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. * The calendar counters are configured to display the calendar digits in BCD format by using the automatic calendar function as follows: The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, ..., 92, and 96 in leap years) and are carried to the /1920 digits in reversion from 99 to 00. The /1920 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data.
D4 Y10 Y10
D3 Y8 Y8
D2 Y4 Y4
D1 Y2 Y2
D0 Y1 Y1
*
Oscillation Adjustment Register (Address 7h) D7 D6 D5 D4 D3 D2 D1 D0 DEV F6 F5 F4 F3 F2 F1 F0 (For Writing) DEV F6 F5 F4 F3 F2 F1 F0 (For Reading) 0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. DEV bit When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds. When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds. F6 to F0 bits The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the settings of the Oscillation Adjustment Register at the timing set by DEV.
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R2043K/T
* * The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the Oscillation Adjustment Register. The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2. The F6 bit setting of 1 causes a decrement of time counts by ((/F5, /F4, /F3, /F2, /F1, /F0) + 1) x 2. The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor decrement of time counts.
Example: If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or 40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss). If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40, neither an increment nor a decrement of the current time counts of 32768. If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a decrement of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain). An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 / (32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. Consequently, when DEV is set to "0", deviations in time counts can be corrected with a precision of 1.5 ppm. In the same way, when DEV is set to "1", deviations in time counts can be corrected with a precision of 0.5 ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-kHz clock pulses. For further details, see "P31 Oscillation Adjustment Circuit".
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R2043K/T
Alarm_W Registers (Address 8-Ah) Alarm_W Minute Register (Address 8h) D7 D6 D5 D4 WM40 WM20 WM10 0 WM40 WM20 WM10 Indefinite Indefinite Indefinite 0 Alarm_W Hour Register (Address 9h) D7 D6 D5 D4 WH20 WH10 WP/A 0 0 WH20 WH10 WP/A Indefinite Indefinite 0 0
D3 WM8 WM8
Indefinite
D2 WM4 WM4
Indefinite
D1 WM2 WM2
Indefinite
D0 WM1 WM1
Indefinite
(For Writing) (For Reading) Default Settings *)
D3 WH8 WH8
Indefinite
D2 WH4 WH4
Indefinite
D1 WH2 WH2
Indefinite
D0 WH1 WH1
Indefinite
(For Writing) (For Reading) Default Settings *)
Alarm_W Day-of-week Register (Address Ah) D7 D6 D5 D4 D3 D2 D1 D0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Writing) 0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Reading) Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) 0 *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. The D5 bit of the Alarm_W Hour Register represents WP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_W Registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (See "P12 Control Register 1 (ADDRESS Eh) (2) /1224: 12-/24-hour Mode Selection Bit") * WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers. *
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R2043K/T
Example of Alarm Time Setting
Alarm Preset alarm time Day-of-week Sun. Mon. WW0 1 1 1 0 1 0 WW1 1 1 1 1 0 1 Tue. WW2 1 1 1 1 0 0 Wed. WW3 1 1 1 1 0 1 Th. WW4 1 1 1 1 0 0 Fri. WW5 1 1 1 1 0 1 Sat. WW6 1 1 1 0 0 0 12-hour mode 10 1 10 hr. hr. min. 1 min. 24-hour mode 10 1 10 hr. hr. min. 1 min.
00:00 a.m. on all days 01:30 a.m. on all days 11:59 a.m. on all days 00:00 p.m. on Mon. to Fri. 01:30 p.m. on Sun. 11:59 p.m. on Mon. ,Wed., and Fri.
1 0 1 3 2 3
2 1 1 2 1 1
0 3 5 0 3 5
0 0 9 0 0 9
0 0 1 1 1 2
0 1 1 2 3 3
0 3 5 0 3 5
0 0 9 0 0 9
Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory. Alarm_D Register (Address B-Ch) Alarm_D Minute Register (Address Bh) D7 D6 D5 D4 DM40 DM20 DM10 0 DM40 DM20 DM10 Indefinite Indefinite Indefinite 0
D3 DM8 DM8
Indefinite
D2 DM4 DM4
Indefinite
D1 DM2 DM2
Indefinite
D0 DM1 DM1
Indefinite
(For Writing) (For Reading) Default Settings *)
Alarm_D Hour Register (Address Ch) D7 D6 D5 D4 D3 D2 D1 D0 DH20 DH10 DH8 DH4 DH2 DH1 (For Writing) DP/A 0 0 DH20 DH10 DH8 DH4 DH2 DH1 (For Reading) DP/A Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *) 0 0 *) Default settings: Default value means read / written values when the PON bit is set to "1" due to VDD power-on from 0v. * The D5 bit represents DP/A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (See "P12 Control Register 1 (ADDRESS Eh) (2) /1224: 12-/24-hour Mode Selection Bit")
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R2043K/T
Interfacing with the CPU
DATA TRANSFER FORMATS (1) Timing Between CE Pin Transition and Data Input / Output The R2043K/T adopts a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output) pins to receive and send data to and from the CPU. The 4-wire serial interface provides two types of input/output timings with which the SO pin output and the SI pin input are synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The R2043K/T is configured to select either one of two different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing with which the SO pin output is synchronized with the rising edge of the SCLK pin input, and the SI pin input is synchronized with the falling edge of the SCLK pin input, as illustrated in the timing chart below.
CE SCLK tDS SI tDH tRD
tCES
SO
Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the timing with which the SO pin output is synchronized with the falling edge of the SCLK pin input, and the SI pin input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below.
CE SCLK tDS SI tDH tRD
tCES
SO
(2) Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the most significant bit (MSB) first.
CE SCLK SI
A3 A2 A1 A0 C3 C2 C1 C0 D7 D6 D3 D2 D1 D0
1
2
3
4
5
6
7
8
1
2
3
Setting the Address Pointer SO
Setting the Transfer Format Register
D7 D6
Writing data transfer
D3 D2 D1 D0
Reading data transfer
Two types of data transfer formats are available for reading data transfer and writing data transfer each.
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R2043K/T
Writing Data Transfer Formats (1) 1-byte Writing Data Transfer Format The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the data transfer format.
Example of 1-byte Writing Data Transfer (For Writing Data to Addresses Fh and 7h)
CE SI SO
Specifying FhSetting 8h in the Transfer in the Address Pointer Format Register Writing data to address Fh Specifying 7h Setting 8h in Writing data to in the Address Pointer the Transfer Format Register address 7h
11111000
Data
01111000
Data
Data transfer from the host
Data transfer from the RTCs
(2) Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be completed by driving the CE pin low.
Example of Burst Writing Data Transfer (For Writing Data to Addresses Eh, Fh, and 0h)
CE SI SO
Specifying EhSetting 0h in Writing data to in the Address Pointer the Transfer Format Register address Eh Writing data to address Fh Writing data to address 0h
11100000
Data
Data
Data
Data transfer from the host
Data transfer from the RTCs
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R2043K/T
Reading Data Transfer Formats (1) 1-byte Reading Data Transfer Format The first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the Address Pointer a head address with which reading data transfer is to be commenced and then the setting of writing Ch to the Transfer Format Register. This 1-byte reading data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the Address Pointer and selecting this type of reading data Transfer Format.
Example of 1-byte Reading Data Transfer (For Reading Data from Addresses Eh and 2h)
CE SI SO
Specifying EhSetting Ch in in the Address Pointer the Transfer Format Register
11101100 Data
Reading data from address Eh
00101100 Data
Specifying 2h Setting Ch in Reading data from in the Address Pointer the Transfer Format Register address 2h
Data transfer from the host
Data transfer from the RTCs
(2) Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be completed by driving the CE pin low.
Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h)
CE SI SO 11110100 DATA
Specifying FhSetting 4h in Reading data from in the the Transfer address Fh Address Pointer Format Register
DATA
Reading data from address 0h
DATA
Reading data from address 1h
Data transfer from the host
Data transfer from the RTCs
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R2043K/T
(3) Combination of 1-byte Reading and writing Data Transfer Formats The 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format.
Example of Reading Modify Writing Data Transfer (For Reading and Writing Data from and to Address Fh)
CE SI SO 11111100 DATA
Specifying FhSetting Ch in Reading data from the Transfer in the address Fh Address Pointer Format Register Specifying FhSetting 8h in in the Address Pointer the Transfer Format Register Writing data to address Fh
11111000
DATA
Data transfer from the host
Data transfer from the RTCs
The reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1 Byte 8h (1,0,0,0) Ch (1,1,0,0) Burst 0h (0,0,0,0) 4h (0,1,0,0)
Writing data transfer Reading data transfer
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R2043K/T
Considerations in Reading and Writing Time Data under special condition Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also occurs in writing time data. To prevent such errors in reading and writing time data, the R2043K/T has the function of temporarily locking any carry to the second digits during the high interval of the CE pin and unlocking such a carry in its high to low transition. Note that a carry to the second digits can be locked for only 1 second, during which time the CE pin should be driven low.
13:59:59 14:00:00 14:00:01
Actual time CE
Max.62s
Time counts within RTC
13:59:59
14:00:00
14:00:01
The effective use of this function requires the following considerations in reading and writing time data: (1) Hold the CE pin high in each session of reading or writing time data. (2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the CE pin low or open at the moment that the host actually goes down. (3) Leave a time span of 31s or more from the low to high transition of the CE pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) Leave a time span of 62s or more from the high to low transition of the CE pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this time span. The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). Good and bad examples of reading and writing time data are illustrated on the next page.
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Good Example
Time span of 31s or more Any address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31 s.
CE SI SO
Address Pointer = Fh Transfer Format Register = 4h
F4h DATA
Reading from Address Fh (control2)
DATA
Reading from Address 0h (sec.)
DATA
Reading from Address 1h (min.)
DATA
Reading from Address 2h (hr.)
Bad Example (1) (Where the CE pin is once driven low in the process of reading time data)
31s or more 31s or more
CE SI SO
Address Pointer = 0h Transfer Format Register = Ch
0Ch Data
Reading from Address 0h (sec.)
14h Data
Address Pointer = 1h Transfer Format Register = 4h Reading from Address 1h (min.)
Data
Reading from Address 2h (hr.)
Bad Example (2) (Where a time span of less than 31s is left until the start of the process of writing time data)
Time span of less than 31s
CE SI SO
Address Pointer = Fh Transfer Format Register = 0h Writing to Address Fh (contorl2) Writing to Address 0h (sec.) Writing to Address 1h (min.) Writing to Address 2h (hr.)
F0h
Data
Data
Data
Data
Bad Example (3) (Where a time span of less than 61s is left between the adjacent processes of reading time data)
Less than 62s
CE SI SO
Address Pointer = 0h Transfer Format Register = Ch
0Ch Data
Reading from Address 0h (sec.)
0Ch Data
Address Pointer = 0h Transfer Format Register = Ch Reading from Address 0h (sec.)
0Ch
Data transfer from the host
Data
Data transfer from RTCs
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R2043K/T
Configuration of Oscillation Circuit and Correction of Time Count Deviations
Configuration of Oscillation Circuit Typical externally-equipped element X'tal : 32.768kHz (R1=50k typ) (CL=6pF to 9pF) Standard values of internal elements CG,CD 10pF typ
OSCIN Oscillator CG Circuit OSCOUT CD
32kHz
A
The oscillation circuit is driven at a constant voltage of approximately 1.1v relative to the level of the VSS pin input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the order of 1.1v on the positive side of the VSS pin input. < Considerations in Handling Crystal Oscillators > Generally, crystal oscillators have basic characteristics including an equivalent series resistance (R1) indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center frequency. Particularly, crystal oscillators intended for use in the R2043K/T are recommended to have a typical R1 value of 50k and a typical CL value of 6 to 9pF. To confirm these recommended values, contact the manufacturers of crystal oscillators intended for use in these particular models. < Considerations in Installing Components around the Oscillation Circuit > 1) Install the crystal oscillator in the closest possible vicinity to the real-time clock ICs. 2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked "A" in the above figure). 3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed circuit board. 4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. < Other Relevant Considerations > 1) For external input of 32.768-kHz clock pulses to the OSCIN pin: DC coupling: Prohibited due to an input level mismatch. AC coupling: Permissible except that the oscillation halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise. 2) To maintain stable characteristics of the crystal oscillator, avoid driving any other IC through 32.768-kHz clock pulses output from the OSCOUT pin.
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R2043K/T
Measurement of Oscillation Frequency
VDD OSCIN
32768Hz OSCOUT 32KOUT VSS Frequency Counter
* 1) * 2)
The R2043K/T is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin. A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit.
Adjustment of Oscillation frequency The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of Model R2043K/T in the system into which they are to be built and on the allowable degree of time count errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system.
Start
Use 32-kHz clock output? YES
YES NO Allowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus NO frequency variations of RTC (*2)? (*3) YES
Course (A)
Course (B)
Use 32-kHz clock output without regard to its frequency precision Course (C) NO YES Allowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus NO frequency variations of RTC (*2)? (*3)
Course (D)
* 1)
* 2) * 3)
Generally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance (CL) and further divided into ranks on the order of 10, 20, and 50ppm depending on the degree of their oscillation frequency variations. Basically, Model R2043K/T is configured to cause frequency variations on the order of 5 to 10ppm at 25C. Time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristics and other properties of crystal oscillators.
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R2043K/T
Course (A) When the time count precision of each RTC is not to be adjusted, the crystal oscillator intended for use in that RTC may have any CL value requiring no presetting. The crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision. Several crystal oscillators and RTCs should be used to find the center frequency of the crystal oscillators by the method described in "P.28 Adjustment of Oscillation frequency" and then calculate an appropriate oscillation adjustment value by the method described in "P.31 Oscillation Adjustment Circuit" for writing this value to the R2043K/T. Course (B) When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the real-time clock ICs, it becomes necessary to correct deviations in the time count of each RTC by the method described in " P.31 Oscillation Adjustment Circuit". Such oscillation adjustment provides crystal oscillators with a wider range of allowable settings of their oscillation frequency variations and their CL values. The real-time clock IC and the crystal oscillator intended for use in that real-time clock IC should be used to find the center frequency of the crystal oscillator by the method described in " P28 Measurement of Oscillation Frequency " and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 0.5ppm. Course (C) Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the crystal oscillator intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing capacitors CG and CD connected to both ends of the crystal oscillator. The R2043K/T, which incorporate the CG and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value. Generally, the relationship between the CL value and the CG and CD values can be represented by the following equation: CL = (CG x CD)/(CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board. The crystal oscillator intended for use in the R2043K/T is recommended to have the CL value on the order of 6 to 9pF. Its oscillation frequency should be measured by the method described in " P.28 Measurement of Oscillation Frequency ". Any crystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit settings disabling the oscillation adjustment circuit (see " P.31 Oscillation Adjustment Circuit") should be written to the oscillation adjustment register. Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor CGOUT or/and CDOUT as illustrated in the diagram below.
*1) The CGOUT or/and CDOUT should have a capacitance ranging from 0 to 6 pF.
OSCIN Oscillator Circuit CG RD CD 32kHz OSCOUT CDOUT CGOUT
However, if adding CGOUT and/or CDOUT, Time keeping Voltage and Current will be worse, and it will be hard to oscillate. For reference, the data of Time keeping voltage and current when adding CGOUT=CDOUT=5pF are shown in the table below. (Topt=-40 to 85C, VSS=0v) PIN Item Condition Min. TYP. MAX. UNITS Vclk Time Keeping CGout=CDout=5pF 1.15 5.5 V Voltage IDD Time Keeping VDD=3V, CE=OPEN, Output=OPEN Current 32KOUT=OFF 0.55 1.20 A CGout=CDout=5pF
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Course (D) It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in the time count of each RTC in the same manner as in Course (B) by the method described in " P.31 Oscillation Adjustment Circuit ".
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R2043K/T
Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation Adjustment Register is set to 0, R2043K/T varies number of 1-second clock pulses once per 20 seconds. When DEV bit is set to 1, R2043K/T varies number of 1-second clock pulses once per 60 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit.
(1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain) When DEV=0: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1) Oscillation frequency x 3.051 x 10-6 (Oscillation Frequency - Target Frequency) x 10 + 1 When DEV=1: Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333) Oscillation frequency x 1.017 x 10-6 (Oscillation Frequency - Target Frequency) x 30 + 1
* 1)
Oscillation frequency: Frequency of clock pulse output from the 32KOUT pin at normal temperature in the manner described in " P.28 Measurement of Oscillation Frequency ". * 2) Target frequency: Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the RTC is expected to be operated. * 3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is represented in 7-bit coded decimal notation. (2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss) Oscillation adjustment value = 0, +1, -64, or -63 (3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency x 3.051 x 10-6 (Oscillation Frequency - Target Frequency) x 10 When DEV=1: Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency x 1.017 x 10-6 (Oscillation Frequency - Target Frequency) x 30 Oscillation adjustment value calculations are exemplified below (A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz When setting DEV bit to 0: Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 x 3.051 x 10-6) (32768.85 - 32768.05) x 10 + 1 = 9.001 9 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. When setting DEV bit to 1:
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R2043K/T
Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 x 1.017 x 10-6) (32768.85 - 32768.05) x 30 + 1 = 23.51 24 In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,0) in the oscillation adjustment register. (B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz When setting DEV bit to 0: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 x 3.051 x 10-6) (32762.22 - 32768.05) x 10 = -58.325 -58 To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128 (80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. When setting DEV bit to 1: Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 x 1.017 x 10-6) (32762.22 - 32768.05) x 30 = -174.97 -175 Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out of range.
(4) Difference between DEV=0 and DEV=1 Difference between DEV=0 and DEV=1 is following, DEV=0 -189.2ppm to 189.2ppm 3ppm DEV=1 --62ppm to 63ppm 1ppm
Maximum value range Minimum resolution
Notes: 1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. 2) If following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. Using oscillator adjustment function 2. Access to R2043K/T at random, or synchronized with external clock that has no relation to R2043K/T, or synchronized with periodic interrupt in pulse mode. 3. Access to R2043K/T more than 2 times per each second on average. For more details, please contact to Ricoh. How to evaluate the clock gain or loss The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit does not effect the frequency of 32768Hz-clock pulse output from the 32KOUT pin. Therefore, after writing the oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The way to measure the clock error as follows: (1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh. (2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure.
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1Hz clock pulse T0 T0 19 times T0 T1 1 time
Measure the interval of T0 and T1 with frequency counter. recommended for the measurement. (3) Calculate the typical period from T0 and T1 T = (19xT0+1xT1)/20 Calculate the time error from T.
A frequency counter with 7 or more digits is
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R2043K/T
Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring
PON, /XST, and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 1.6 or 1.3v. Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and /XST bit is for the oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to "H". However, /XST bit is activated to "L". The PON and VDET accept only the writing of 0, but /XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0, and /XST is indefinite. The functions of these three monitor bits are shown in the table below. PON Monitoring for the power-on reset function D4 in Address Fh High 1 0 only /XST Monitoring for the oscillation halt sensing function D5 in Address Fh Low indefinite Both 0 and 1 VDET a drop in supply voltage below a threshold voltage of 1.6 or 1.3v D6 in Address Fh High 0 0 only
Function
Address Activated When VDD power up from 0v accept the writing
The relationship between the PON, /XST, and VDET is shown in the table below. PON 0 /XST 0 VDET 0 Conditions of supply voltage and oscillation Halt on oscillation, but no drop in VDD supply voltage below threshold voltage Halt on oscillation and drop in VDD supply voltage below threshold voltage, but no drop to 0V No drop in VDD supply voltage below threshold voltage and no halt in oscillation Drop in VDD supply voltage below threshold voltage and no halt on oscillation Drop in supply voltage to 0v Condition of oscillator, and back-up status Halt on oscillation cause of condensation etc. Halt on oscillation cause of drop in back-up battery voltage Normal condition
0
0
1
0
1
0
0
1
1
No halt on oscillation, but drop in back-up battery voltage Power-up from 0v,
Threshold voltage (1.6v or 1.3v)
1
*
*
VDD 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (/XST) Supply voltage monitor flag (VDET) VDET0 /XST1 PON0 VDET0 /XST1 PON1 VDET0 /XST1 PON0
Internal initialization period (1 to 2 sec.)
Internal initialization period (1 to 2 sec.)
When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, /1224, /CLEN2, TEST,
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CT2, CT1, CT0, VDSL, VDET, /CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0v. < Considerations in Using Oscillation Halt Sensing Circuit > Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the VDD 2) Condensation on the crystal oscillator 3) On-board noise to the crystal oscillator 4) Applying to individual pins voltage exceeding their respective maximum ratings In particular, note that the /XST bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit.
VDD
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Voltage Monitoring Circuit The supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 1.6 or 1.3v for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the Control Register 2. The supply voltage monitor is useful for back-up battery checking.
VDD 1.6v or 1.3v PON
Internal initialization period (1 to 2sec.)
7.8ms 1s
Sampling timing for VDD supply voltage VDET (D6 in Address Fh) VDET0
PON0 VDET0
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R2043K/T
Alarm and Periodic Interrupt
The R2043K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the /INTR pin as described below. (1) Alarm Interrupt Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the /INTR, which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings). (2) Periodic Interrupt Circuit The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the /INTR pin depending on the CT2, CT1, and CT0 bit settings in the control register 1. The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control Register 1) as listed in the table below. Flag bits WAFG (D1 at Address Fh) DAFG (D0 at Address Fh) CTFG (D2 at Address Fh) Enable bits WALE (D7 at Address Eh) DALE (D6 at Address Eh) CT2=CT1=CT0=0 (These bit setting of "0" disable the Periodic Interrupt) (D2 to D0 at Address Eh)
Alarm_W Alarm_D Peridic interrupt
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the /INTR pin is driven high (disabled). * When two types of interrupt signals are output simultaneously from the /INTR pin, the output from the /INTR pin becomes an OR waveform of their negative logic.
Example: Combined Output to /INTR Pin Under Control of /ALARM_D and Periodic Interrupt /Alarm_D Periodic Interrupt /INTR
In this event, which type of interrupt signal is output from the /INTR pin can be confirmed by reading the DAFG, and CTFG bit settings in the Control Register 2. Alarm Interrupt The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time.
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The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupts circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function.
Interval (1min.) during which a match between current time and preset alarm time occurs
/INTR
WALE1 current time = WALE0 preset alarm time (DALE) (DALE)
WALE1 (DALE)
current time = preset alarm time
/INTR
WALE1 current time = preset alarm time (DALE)
WAFG0 (DAFG)
current time = preset alarm time
After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, /INTR will be not driven to "L" immediately, /INTR will be driven to "L" at next alarm setting time. Periodic Interrupt Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High (OFF). CT2 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 Description Wave form mode Pulse Mode *1) Pulse Mode *1) Level Mode *2) Level Mode *2) Level Mode *2) Level Mode *2)
Interrupt Cycle and Falling Timing OFF(H) Fixed at "L" 2Hz(Duty50%) 1Hz(Duty50%) Once per 1 second (Synchronized with Second counter increment) Once per 1 minute (at 00 seconds of every Minute) Once per hour (at 00 minutes and 00 Seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month)
(Default)
*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit /INTR Pin Approx. 92s (Increment of second counter) Rewriting of the second counter
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In the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the /INTR pin low. *2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit /INTR Pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The "L" period of output pulses will increment or decrement by a maximum of 3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms. 32-kHz CLOCK OUTPUT For the R2043K/T, 32.768-kHz clock pulses are output from the 32KOUT pin when either the /CLEN1 bit in the Control Register 2 or the /CLEN2 bit in the Control Register 1 is set to 0. When both the /CLEN1 and /CLEN2 bits are set to 0, the 32KOUT pin output is driven high (off). /CLEN1
(D3 at Address Fh)
/CLEN2
(D4 at Address Eh)
1 0(Default) *
1 * 0(Default)
32KOUT PIN (N-channel Open Drain) OFF(H) Clock pulses
The 32KOUT pin output is synchronized with the /CLEN1 and /CLEN2 bit settings as illustrated in the timing chart below.
/CLEN1or2
32KOUT PIN
Max.62.0s
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Typical Applications
Typical Power Circuit Configurations Sample circuit configuration 1 *1) Install bypass capacitors for high-frequency and low-frequency applications in parallel in close vicinity to the R2043K/T.
System power supply OSCIN OSCOUT VDD 32768Hz
*1)
VSS
Sample circuit configuration 2
OSCIN OSCOUT VDD 32768Hz
System power supply
*1) When using an OR diode as a power supply for the R2043K/T ensure that voltage exceeding the absolute maximum rating of VDD+0.3v is not applied the 32KOUT pin.
*1)
VSS
Primary Battery
OSCIN OSCOUT VDD 32768Hz
System power supply
*1)
VSS
Secondary Battery
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R2043K/T
Connection of /INTR and 32KOUT Pin The /INTR pin follows the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5v regardless of supply voltage. The 32KOUT pin follows the N-channel open drain output logic, too. However, it contains protective diode on the power supply side. As such, it cannot be connected to a pull-up resistor over VDD+0.3v. Such connection involves considerations for the supply current requirements of a pull-up resistor, which can be roughly calculated by the following equation: I = 0.5 x (VDD or VCC) / Rp
System power supply (VDD) A *1) B OSCIN OSCOUT VSB VSS 32768Hz Backup power supply (VCC)
/INTR or 32KOUT
*1) Depending on whether the /INTR or 32KOUT pins are to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) Position A in the left diagram when it is not to be used during battery backup. (2) Position B in the left diagram when it is to be used during battery backup.
Connection of CE Pin Connection of the CE pin requires the following considerations: 1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be driven low or open at power-on from 0v. 2) The CE pin should also be driven low or open immediately upon the host going down (see "P.25 Considerations in Reading and Writing Time Data under special condition").
SCLK I/O CONTROL SI
Lower limit operating voltage for the CPU VDD Backup power supply 0.2xVDD
SO
CE
CE
Min.0s
Min.0s
Min.0s
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R2043K/T
Connection With 3-Wire Serial Interface Bus To connect the R2043K/T with 3-wire serial interface bus, shorten the SI and SO pins and connect them to the data line as shown in the figure below.
CE0 Host CE1 SCLK DATA
CE SCLK R2043 SI SO
CE SCLK The other SIO Peripheral IC
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R2043K/T
Typical Characteristics
Test circuit
VDD OSCIN CGOUT 32768Hz OSCOUT CDOUT 32KOUT VSS Frequency Counter
X'tal : 32.768kHz (R1=50k typ) (CL=6pF to 9pF) Topt : 25C Output pins : Open
Timekeeping Current vs. Supply Voltage (with no 32kHz clock output) (CE=Open, Output=Open, Topt=25C)
Timekeeping Current IDD(uA)
Timekeeping Current vs. Supply Voltage (with 32kHz clock output) (CE=Open, Output=Open, Topt=25C)
Timekeeping Current IDD(uA)
1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 Supply Vlotage VDD(v)
1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 Supply Voltage VDD(v)
(CGout, CDout)=(5pF, 5pF) (CGout, CDout)=(0pF, 0pF)
(CGout, CDout)=(5pF, 5pF)
(CGout, CDout)=(0pF, 0pF)
CPU Access Current vs. SCLK Clock Frequency (Output pins=Open, Topt=25C, CGout=CDout=0pF)
CPU Access Current IDD(uA)
Timekeeping Current vs. Operating Temperature (CE=Open, Output pins=Open, CGout=CDout=0pF)
Timekeeping Current IDD(uA)
80 70 60 50 40 30 20 10 0 0 200
1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 Operating Temperature Topt(Celcius)
VDD=5v
with 32kHz clock output with no 32kHz clock output
VDD=3v
400
600
800
1000
SCLK Clock Frequency (kHz)
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Oscillation Frequency Deviation vs. External CF, CD (VDD=3v, Topt=25C, CGout=CDout=0pF as standard)
Oscillation Frequency Deviation (ppm)
Oscillation Frequency Deviation vs. Supply Voltage (Topt=25C,VDD=3v as standard)
Oscillation Frequency Deviation (ppm)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5
CDout=0pF
CDout=5pF
5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1 2 3 4 5 6 Supply Voltage VDD (v)
10
15
20
External CG (pF)
Oscillation Frequency Deviation vs. Operating Temperature (VDD=3v, Topt=25C as standard)
Oscillation Frequency Deviation (ppm)
VOL vs. IOL (32KOUT) (Topt=25C)
20 0 -20 -40 -60 -80 -100 -120 -60 -40 -20 0 20 40 60 80 10 0 Operating TemperatureTopt(Celsius)
7 6 5
IOL (mA)
VDD=5v VDD=3v VDD=1.5v
0 0.1 0.2 0.3 0.4 0.5
4 3 2 1 0 VOL (v)
VOL vs. IOL (/INTR pin) (Topt=25C)
30 25
IOL(mA)
20 15 10 5 0 0 0.1 0.2 0.3
VDD=5v VDD=3v VDD=1.5v
0.4 0.5
VOL(v)
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Typical Software-based Operations
Initialization at Power-on
Start *1) Power-on *2)
PON=1?
No *3)
VDET=0?
Yes
*4) Yes
Set Oscillation Adjustment Register and Control Register 1 and 2, etc.
No
Warning Back-up Battery Run-down
*1) *2) *3) *4)
After power-on from 0 volt, the start of oscillation and the process of internal initialization require a time span on 1to 2seconds, so that access should be done after the lapse of this time span or more. The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not PON, /XST, and VDET". from 0v. For further details, see "P.34 This step is not required when the supply voltage monitoring circuit is not used. This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt cycle settings, etc.
Writing of Time and Calendar Data
*1) When writing to clock and calendar counters, do not drive CE to "L" until all times from second to year have been written to prevent error in writing *2) Considerations in Reading and Writing time. (Detailed in "P.24 Write to Time Counter and Time Data under special condition ". Calendar Counter
CE H
*1)
CE L
*3)
*2) Any writing to the second counter will reset divider units lower than the second digits. *3) Take care so that process from CE driving to "H" to driving to "L" will be complete within 1.0sec. (Detailed in "P.24 Adjustment of Oscillation
frequency".
The R2043K/T may also be initialized not at power-on but in the process of writing time and calendar data.
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Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data
CE H
*1)
*1) When writing to clock and calendar counters, do not insert Stop Condition until all times from second to year have been written to prevent error in writing time. (Detailed "P.24 Considerations in Reading and Writing
Read from Time Counter and Calendar Counter
Time Data under special condition".
*2) Take care so that process from Start Condition to Stop Condition will be Considerations in complete within 0.5sec. (Detailed in "P.24
Reading and Writing Time Data under special condition".
CE L
*2)
(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function
Set Periodic Interrupt Cycle Selection Bits *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 1.0 second. *3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.
*1)
Generate Interrupt in CPU
CTFG=1?
No *2)
Yes
Read from Time Counter and Calendar Counter
Other Interrupt Processes
*3)
Control Register 2 (X1X1X011)
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(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:
Control Register 1 (XXXX0100) Control Register 2 (X1X1X011)
*1)
Generate interrupt to CPU Other interrupts Processes
CTFG=1?
No *2)
Yes
Sec.=00?
*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 1.0 sec. *3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.
No *3)
Use previous Min.,Hr., Day, and Day-of-week data
Yes
Read Min.,Hr.,Day, and Day-of-week
Control Register 2 (X1X1X011)
*4)
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Interrupt Process (1) Periodic Interrupt
Set Periodic Interrupt Cycle Selection Bits
*1)
*1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU.
Generate Interrupt to CPU
CTFG=1? Yes
Conduct Periodic Interrupt
No
Other Interrupt Processes
*2)
Control Register 2 (X1X1X011)
(2) Alarm Interrupt
WALE or DALE0
*1)
Set Alarm Min., Hr., and Day-of-week Registers
WALE or DALE1
*2)
*1) This step is intended to once disable the alarm interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) This step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) This step is intended to once cancel the alarm interrupt function by writing the settings of "X,1,X, 1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W Registers and the Alarm_D Registers, respectively.
Generate Interrupt to CPU
WAFG or DAFG=1?
No Other Interrupt
Processes
Yes
Conduct Alarm Interrupt
*3)
Control Register 2 (X1X1X101)
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